Mobile communication is becoming increasingly popular. The recent revolution in digital processing has enabled a rapid migration of mobile wireless services from analog communications to digital communications. For example, cellular service providers have already deployed substantial digital wireless communication infrastructure, much of which utilizes code division, multiple access (CDMA) technology. Increasingly, development efforts are focusing on techniques for high-capacity communication of digital information over wireless links, and much of this broadband wireless development work incorporates spread-spectrum communications similar to those used in CDMA.
Spread-spectrum is a method of modulation, like FM, that spreads a data signal for transmission over a bandwidth, which substantially exceeds the data transfer rate. Direct sequence spread-spectrum involves modulating a data signal onto a pseudo-random chip sequence. The chip sequence is the spreading code sequence, for spreading the data over a broad band of the spectrum. The spread-spectrum signal is transmitted as a radio wave over a communications media to the receiver. The receiver despreads the signal to recover the information data.
The attractive properties of these systems include resistance to multipath fading, soft handoffs between base stations and interference resistance. In addition, in a multipath environment, the use of Rake receivers enables the harnessing of the total received energy.
Receiving the direct sequence spread spectrum communications requires detection of one or more spreading chip-code sequences embedded in an incoming spread-spectrum signal as well as subsequent synchronization of the receiver to the detected chip-code sequence. Initial detection and phase synchronization of the spreading chip-code sequence(s) in the receiver is commonly known as code acquisition. Although simple correlators have been used in the code acquisition for reception of spread-spectrum signals, faster and more efficient techniques for code acquisition rely on matched filters.
A matched filter essentially matches elements or samples of an input signal to elements of a reference chip-code sequence signal, by multiplying a set of N samples of the input signal with a corresponding number of values of the reference signal, then summing the product terms to determine a value of correlation of the set of samples of the input signal to the reference signal. For a single code sequence, if the correlation value exceeds a threshold, then a decision circuit indicates that there is a match. If there are a plurality of spreading codes that may be used in the communication system, the receiver typically uses a bank of matched filters for parallel matching to a corresponding plurality of reference codes. If the receiver expects to receive only one transmission at a time, the decision processor selects the reference code having the highest correlation to the input samples as the match to the code contained in the received spread-spectrum signal. In many applications, the matching operations indicate how many possible spreading code sequences are received in a given symbol interval.
FIG. 6 is a simplified diagram of a matched filter. Specifically, the block diagram shows a layered matched filter structure. For purposes of this example, assume that the spreading code sequence and the corresponding reference are each 16-chips long. The matched filter therefore is scaled to match sixteen input samples to the 16-chip reference code. The input signal is initially applied to a multi-tap delay line formed of a series of fifteen delay devices 1. The matched filter comprises a plurality of multipliers 3. The filter includes one such multiplier 30 to 315 for receiving each of the input chip sequences from the input and the fifteen taps between and after the delays 11 to 115 of the delay line.
Assume for discussion purposes that each reference code comprises a sequence T0, T1. . . r15. Each multiplier 3 receives a portion ri of reference code of the particular sequence for multiplication with the respective current or delayed portion Xi of the input chip stream. Thus, the multiplier 30 receives the r0 value of the reference code and multiplies it by the X0 sample of the input (i.e. the current sample). Similarly, the multiplier 31 receives the r1 value of the reference code and multiplies it by the X1 sample of the input (i.e. the sample from the previous time interval delayed by the device 11); and so on until the multiplier 315 receives the r15 value of the reference code and multiplies it by the X15 sample of the delayed input as received from the delay device 115.
Assuming that a code chip may have a value of 1 or −1 (corresponding to 0, 1 in digital/binary notation), each multiplication operation will have an output value of 1 if the input value and the reference value are the same (1×1 or −1×−1). Each multiplication operation will have an output value of −1 if the input value and the reference value are different (1×−1 or −1×1).
To determine an overall correlation to the complete reference code sequence, the outputs of the multipliers 30 to 315 are summed in pairs, through layers of adders 5, 7 and 9 arranged in a tree structure. The last adder 9 outputs the total correlation value, which represents how closely the input chip stream matched the reference code sequence. For a perfect match, for example, the output of the adder 9 would be equal to the number N of chips matched, that is to say 16 in the present example. If there were no match at all, the output of the adder 9 would be −16. However, in an implementation processing real received spread-spectrum signals, there will be some variable degree of matching.
FIG. 7 shows a modified form of a matched filter, which makes the device programmable. Again in a 16-chip example, the input signal is initially applied to a multi-tap delay line, in this case a line formed of a series of fifteen delay devices 11. The matched filter comprises sixteen multipliers 130 to 1315, that is to say one for receiving each of the input chip samples X0 to X15 from the input and the taps between and after the delays 111 to 1115 of the delay line. In this implementation, however, each multiplier 13 multiplies the respective sample from the input by a value of −1. In an actual circuit, a simple inverter circuit can implement each operation of multiplication by factor −1.
The programmable matched filter also comprises a plurality of selector circuits (SELs) 15. The filter includes one such selector (SEL) 150 to 1515 for receiving each of the input chip samples X0 to X15 from the input and the taps of the delay line. Each selector 15 receives a respective sample Xi on its 0 input port. A respective multiplier/inverter 13 supplies the inverse of that sample value or −Xi to the 1 input port of the respective selector 15. In the programmable version of the matched filter, the reference code components r0, r1. . . r15 are applied to respective control inputs of the selectors (SEL) 150 to 1515. In the programmable device of FIG. 7, each combination of a multiplier/inverter 13 with a selector 15 essentially replaces one of the code multipliers 3 in the embodiment of FIG. 6.
Assuming again that a code chip may have a value of 1 or −1 (corresponding to 0, 1 in binary notation), each selector 15 outputs a value of 1 if the input value and the reference value are the same (1×1 or −1×1). Each selector 15 outputs a value of −1 if the input value and the reference value are different (1×−1 or −1×1).
To achieve this operation, each selector (SEL) 150 to 1515 receives a portion ri of reference code of the particular sequence. In response, each selector outputs the current value of Xi from the 0 input port or the current value −Xi appearing at the 1 input port, based on the current value of the respective ri portion of the reference code sequence. More specifically, if the binary value of ri=1, a selector 15 will supply the input from port 1 to its output, that is to say the inverse of the respective sample value Xi. Conversely, if the binary value of ri=0, a selector 15 will supply the input from port 0 to its output, that is to say the actual respective value Xi. For example, the selector 150 receives the r0 value of the reference code and outputs the X0 sample of the input if the r0 value has a binary value of 0 signifying a positive (+1) input. The selector 150 outputs the −X0 sample of the input if the r0 value has a binary value of 1 signifying a negative (−1) input.
Consequently, if the reference binary value is ri=0 (signal level of +1), the selector outputs a +1 if the input signal Xi=1 and thereby matches the reference. Similarly, if the binary reference value is ri=1, the selector outputs a +1 taken from the −Xi input, when the input signal Xi=−1 and thereby matches the reference. Conversely, the selector outputs a −1 when the binary value of ri=0 (signal level of +1) and the input signal of Xi=−1. The selector similarly outputs a −1 when the binary value of ri=1 (representing a signal level of −1) and the input signal Xi=1.
To determine an overall correlation of the set of samples to the complete set of values of the reference code sequence, the outputs of the selectors 15 are summed, in this case through a series of adders 171 to 1715. The last adder 1715 outputs the total correlation value, which represents how closely the input chip stream matched the current reference sequence r, essentially as in the embodiment of FIG. 6. The use of the selectors 15, however, makes the matched filter of FIG. 7 programmable, in that it is a simple matter to reprogram the filter by changing the ri values of the binary sequence appearing on the control inputs of the selector circuits 15.
The receiver circuitry, including that of the matched filters may be implemented in the form of a programmable digital signal processor, but more often is implemented in an application specific integrated circuit (ASIC) chip. Each inversion and each addition requires a processor operation or more likely a circuit module within the ASIC. Each inverter or adder increases the complexity of design and manufacture of the chip. Also, each inverter or adder consumes space on the actual chip and requires additional power, both of which are scarce resources, particularly in a mobile wireless receiver.
There is an ongoing need to improve the efficiency of the receiver circuitry, including that of the matched filter(s). The need is multiplied when multiple filters are used in a bank for processing code sequences in parallel. The problems also grow as the filter design expands to handle longer code sequences. Hence there is a clear need for a technique to simplify the structure and operation of a programmable matched filter, particularly one used to implement the matched filter bank in a mobile spread-spectrum receiver.